As integrated circuits have become more complex employing more and more pins in a limited area, mutual inductance between pins has increased. In fact, a complex integrated circuit die is conventionally coupled to a significantly larger package to couple such integrated circuit die to a printed circuit board (“PCB”), as the pin density of such die may be too great to directly couple the die to the PCB.
To address mutual inductance, as well as self-inductance, in interconnect arrays and other interconnect topologies, others have suggested using patterns to lay out such interconnect arrays. One type of pattern known as a checkerboard pattern conventionally alternates power and ground pins to reduce mutual inductance; however, the checkerboard pattern leaves no pins for signals.
Accordingly, it would be desirable and useful to provide a pinout with sufficiently low mutual inductance, but with increased signal pin density over that of a checkerboard pattern.